1. Field of the Invention
This invention relates generally to photolithography techniques for patterning semiconductor devices, and, more particularly, to a method for controlling photoresist strip processes.
2. Description of the Related Art
Conventionally, semiconductor devices are patterned using photolithographic processes. A base material, such as a substrate material, a metal, an insulator, etc., is coated with a light sensitive material, referred to as a photoresist material. The photoresist is generally a composition that is sensitive to active rays of light, such as ultraviolet rays, X-rays or electron rays. The photoresist is deposited on the base material to selectively protect non-process portions of the substrate. Light is then selectively directed onto the photoresist film through a photomask, or reticle, to form photoresist patterns on the base material. The photoresist is then developed to remove either the exposed photoresist or the unexposed photoresist.
There are generally two types of photoresist, namely positive type and negative type. The positive photoresist is of such a type that the exposed portion dissolves in the developer, while the unexposed portion does not dissolve therein, and the negative photoresist is of the opposite type. Certain photoresist materials do not complete the transition from being soluble to being insoluble in the developer based solely on the exposure to light. These photoresist materials, referred to as chemically-amplified photoresists, are subjected to a post exposure bake process to complete the chemical reaction to transition from soluble to insoluble (i.e., for a positive resist).
The process of using a chemically-amplified photoresist is described in greater detail in reference to FIGS. 1A through 1D. FIG. 1A shows a wafer 10 including a base material 12 with a photoresist layer 14 deposited thereon. In FIG. 1B, the photoresist layer 14 is exposed to a light source through a photomask (not shown) to define exposed regions 16. Exposure to the light causes hydrogen free radicals to form in the exposed regions 16, which are on the surface of the photoresist layer 14. In FIG. 1C, the wafer 10 is subjected to a post exposure bake to complete the solubility transition chemical reaction and form baked regions 18. During the post exposure bake, the free radicals diffuse downward and react with the photoresist 14 beneath the exposed regions 16. Typically, for a deep UV photoresist layer 14, the post exposure bake time is about 60-90 seconds. As shown in FIG. 1D, a developer may then be applied to remove the remaining photoresist 14 (i.e., for a negative resistxe2x80x94shown in FIG. 1D) or to remove the baked portions 18 (i.e., for a positive resistxe2x80x94not shown).
Typically, the wafer 10 is subject to additional processing, such as deposition of another layer, implantation, etching, etc. using the pattern defined by the photolithography process described above. Following the additional processing; the remaining photoresist (i.e., in the baked regions 18) is stripped using a process such as a plasma etch or a wet etch. The plasma strip tool uses plasma-enhanced, ionized oxygen/oxygen radicals. A wet etch tool typically uses sulfuric acid/peroxide mixes followed by rinses or a sequence of standard cleans.
The photoresist may also be stripped at some point in the photolithography process to allow re-work (e.g., re-coating, exposing, and developing) of the wafer due to poor processing in one of the previous photolithography steps. For example, an overlay or critical dimension measurement performed after one of the intermediate photolithography steps may identify that the photoresist pattern is not suitable for further processing. Such a condition might have been caused by a defect, miscalibration, or other such processing problem in the stepper or developer, for example.
Accurate control of the stripping process is important for preventing defects in the wafer. If the photoresist strip time is too short (i.e., understripping), remnants of the photoresist layer will be present on the wafer, interfering with subsequent processing steps. If the strip time is too long (i.e., overstripping), the wafer may be damaged by unnecessary exposure to ion charging effects, and also the processing time for completing the wafer is lengthened. Typically, a minimum strip time designed to provide a certain amount of overstripping to ensure complete removal of the photoresist is programmed into the recipe of the developer. However, variations in the photoresist, developer, photoresist layer thickness, etc., may result in different photoresist strip rates for various wafers in the same or different lots. Accordingly, a minimum strip time does not always ensure that all of the photoresist is removed. Raising the strip time to encompass such process variations could result in wafer damage and lengthen processing time.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for fabricating wafers. A photoresist layer is formed on a wafer. A first thickness of the photoresist layer is measured, and a portion of the photoresist layer is removed. A second thickness of a remainder portion of the photoresist layer is measured. A photoresist strip rate is determined based on the first and second thicknesses, and a recipe of a developer is modified based on the photoresist strip rate.
Another aspect of the present invention is seen in a wafer processing system including a stepper, a developer, and an automatic process controller. The stepper is adapted to expose a wafer having a photoresist layer deposited thereon. The developer is adapted to remove at least a portion of the photoresist layer based on a recipe. The process controller is adapted to receive a photoresist strip rate and modify the recipe based on the photoresist strip rate.